PART TWO.

LOW COST IMAGE PROCESSING

Vision is the greatest gift of life. It is also the most complicated interface between an animal and its environment, and with the highest information bandwidth. Image processing is basically a simulation of our vision system, opening a real window in the computer to obtain real information from the real world. Because of the high information bandwidth and the large amount of data to be stored and processes in real time, image processing has been a very expensive proposition. Ten years ago when I first got involved in this subject, an image processing which can handle images of 512 by 512 pixels of 8 bits data cost almost 1 million dollars. Only big government agencies, big companies, and big universities could afford them. The reason was very simple. Image processor depends upon fast RAM memory chips for storage and processing, and needs lots of them, in the order of mega bytes. As the cost of RAM is reduced by 50% every year, the price of image processors are driven down at roughly the same rate. Ten years later, now the cost of a simple image processor is about one thousand dollars, very close to the threshold of pain for personal computer enthusiasts. As the price drops, we will see more people using them to do innovative things unimaginable to computer scientists.

These low cost image processors come in the form of plug-in boards which can be plugged into low cost personal computers and give these computers eyes to see real things. The users thus get powerful tools to manipulate image data, extract meaningful information from the images, and to create new images to convey new ideas and impressions. Many companies are producing image processors for different microcomputers. We have seen products based on DEC's Q-bus, Intel's Multibus, Motorola's VME bus, the old S-100 bus, and more recently, the ubiquitous PC bus.

It is easy to confuse graphic processors with image processors. Most personal computers nowadays has good graphics capability, capable of displaying lines and shapes in grey levels or in color. However, these graphic processors can only display synthetic images generated by the computer, and they can not import or export images very conveniently from or to standard video equipment, like TV monitors, video recorders, and video cameras. To be called an image processor, it must be able to interface to one or more of these video equipment using NSTC TV standard format. A TV frame contains about 500x500 or 250,000 pixels refreshed at a rate of 30 Hz. It translates to 250,000 bytes of data transmitted at a rate of 10 MHz. An image processor must be able to handle that amount of data at that speed, which is not a trivial task. This is the reason why image processors have to be specialized processing elements surrounded by large amount of fast memory.

I had the good fortune to gain access to many of them. The manufacturers generally provide some software with the image processor boards, containing utility to let you use the boards quickly, and some form of library for those who incline to program them. My tendency is to ignore these software but concentrate on their hardware manuals. Once I learn the internal structures and the interface protocols, I can talk to these boards more fluently in Forth and solve my problem more quickly.

I presented an image processing package for the IP5500 image processor from DeAnza, which is now part of Gould, in the first volume of 'Forth Notebook'. IP5500 was a second generation image processing, a good state of the art system eight years ago with a price tag of about $50,000. I used it to simulated the GAPP parallel processor. Shortly after that it was junked. In this volume I will report my experience with three newer, and much less expensive image processors: CAT 1600 from Digital Graphic Systems, QVG-123 from DataCube, and PIP-1024 from Matrox.

Programming these image processors with Forth is very pleasant. My first step was to find the descriptions on the command register, the status register, and the data register in them. Next, I defined these registers as constants and tried to exercise the command register to do some thing which modified the displayed image on CRT, such as writing a write dot, erasing a line, or putting a character on CRT. These experiments taught me how to converse with the image processor board, so that I could write the basic interface routine. After that, I would write a few demonstration routines to impress people around me. Color look up tables were always fun. Splashing colors on the CRT screen always attracts people's attention. The last fun thing was hooking a TV camera to the image processor and let people process their own portraits. After that, well, get on the project which pays the bill.

CHAPTER 6.

DATACUBE QVG-123 IMAGE PROCESSOR

1. QVG-123 IMAGE PROCESSOR BOARD

QVG-123 Board is manufactured by Datacube, Inc. in Peabody, MA. Datacube has specialized in low cost imaging boards for mini- and micro-computers for some time. Lately, it got more ambitious and developed quite sophisticated image processing systems for VME bus computers. QVG-123 was one of its earlier products for DEC Q-bus microcomputers like LSI-11/04 and its family members.

QVG-123 provides a full screen of image memory for computer generated or digitized images. Either black/white or RGB pseudo color display is available, with intensity transformation tables for the video input and the three output channels. A character overlay of 24 lines of 80 characters is also included.

The image memory on the QVG-123 board itself is arranged in the form of 768x512x4 bits. A piggy-back board AF-123 adds 4 bits to each pixel, so that the intensity resolution can be increased to 8 bits or 256 grey levels. The image memory can be accessed by the host computer through a pair or X,Y address registers and a data register. The address registers can be incremented automatically after each access, allowing for high speed sequentially memory access.

One video input source is selected through software from four input channels to the high speed A/D converter for image digitization. The A/D converter runs at a rate of 14.3 MHz with 8 bit of resolution. The input is of the RS-170 format, common to most video cameras and other standard video devices. The timing of the video circuitry can be selected from an internal crystal oscillator, or from an external video sync source. An enhanced phase-lock-loop circuit assures the stability when using external sync source.

The composite video outputs are compatible to EIA standards, either the interlaced RS-170 or non-interlaced RS-420. Separated horizontal and vertical sync signals are TTL compatible. QVG-123 produces three channels of 4 bit video outputs. With AF-123, 8 bit video outputs replace the 4 bit outputs. The character overlay signal is available as an independent output on QVG-123.

2. PROGRAMMING MODEL

The QVG-123 board occupies 9 16 bit registers in the I/O space on the DEC Q-bus. The address is normally set at 176000 to 176020 octal, but can be changed by on board jumpers. AF-123 adds 5 more registers immediately after the QVG-123 registers. The location and bit or field definitions of the QVG-123 registers are shown in Figure 8, and those of AF-123 are shown in Figure 9.

The data register is used in conjunction with the horizontal and vertical position registers to read or write the image memory. Image data can be accessed either by 16 bit words or by 8 bit bytes. Using the data register at 176000, the data transfer is 16 bits at a time. Using the data register at 176001, the transfers are in bytes.

Pan and scroll registers allow the image to be shifted in the horizontal or vertical directions. The character address and character data registers are used to read or write the character overlay memory for displaying ASCII characters on the display.

The command and status register is the most complicated register to deal with. The individual bits in this register controls the memory access mode, horizontal and vertical zoom, selecting video inputs, handling and monitoring interrupts, selecting output look-up tables, and selecting character overlay modes. Most of the programming efforts are concentrated in this register.

QVG-123 also allows individual image memory planes to be protected from accidental writing. Two 8 bit masks in the write enable register can be programmed to enable or disable bit-planes in the image memory to receive or ignore data from the A/D converter or from the host.

The command/status register 2 on AF-123 selects the input channel, the input look-up tables and the output look-up tables. These look-up tables are initialized through the red, green, and blue output LUT registers, and the input LUT register.

To program this QVG-123/AF-123 image processor is to write bit patterns into one or more of these registers, and to monitor the status by reading some other registers. In a Datacube data sheet, there is a outline of several procedures to use this imaging system. The outline is shown in Figure 10.

3. FORTH SOURCE CODE

The host computer used to control this QVG-123/AF-123 board set was a LSI-11/23 clone, manufactured by Scientific Micro Systems in Mountain View, CA. This system was much cheaper than the genuine DEC product. The other advantage in the clones was that they could format floppy disks, while the DEC drives did not allow this heretical practice, in favor of supporting its users with high quality, and thus grossly overpriced, preformatted disks. In stead of buying the equally overpriced operating system and language tools from DEC, we installed polyForth II on the computer as the programming environment.

The programs shown in Listing 8 were all written under polyForth II. The source code was only recently moved to an IBM PC clone so that shadow screens could be added. However, polyForth II is very close to Forth-79 and Forth-83 standards and the words used in this system were restricted to the small set common to all the recent standards.

Since the shadow screens provide lots of comments on the functions and behavior of the words defined in this system, I will restrict myself only to highlight the structure of the system.

Screen 40 contains the definitions of all the registers in QVG-123 and AF-123. They are constants leaving their register address on the stack for fetching or storing.

Screen 41 tests my ability to write directly into the image memory. It ends with a demonstration program WEDGES which paints a linearly shaded image on the display.

Screen 42 has words which manipulate the look-up tables for pseudo coloring and also for image enhancements. CORRECTION computes an output byte from an input byte, according to an S-shape intensity transformation curve using the contrast and brightness values stored in #GAIN and #OFFSET. RAMP fills a look-up table with values generated by CORRECTION. DARK clears a look-up table to wipe out a channel. The utility words BW load all three channels with the same look-up table so that the eight bit image is displayed in black and white. RED, GREEN, or BLUE writes a ramp function into only one channel and darken the other two channels. The result is a grey scale image with one color, red, green, or blue.

Since the application intended for this system would involve lots of real time graphic display, we needed a very fast routine to draw straight lines. Screens 43 to 47 contain an implementation of Bresenham's line-drawing algorithm, which is fast because it avoids multiplication and division in calculating the coordinates of points along the straight line between two arbitrary points on the display. Screen 49 has a routine which draws a rectangle from two diagonal points.

Screens 50 to 52 are programs which move data from disk or memory to the image memory and vice versa.

WRAPPING in Screen 53 sets up the color look-up tables to display rainbow like color spectrum. The red part or green part of the spectrum can be enhanced by the words MORERED or MOREGREEN.

3DEMO is Screen 54 is an interesting demonstration which draws random boxes on the display with random colors. The word FILL-IN fills a box with a color by deposit a byte into all the memory locations within a rectangle box.

Screen 55 controls the video A/D converter. BLANKING tests the vertical blanking bit in the command/status register and freezes on frame of image in the image memory before it exits. VIDEO digitizes the real time image and display them at the 30 Hz video rate. Whenever a key on the terminal keyboard is pressed, the displaying loop terminates and the last frame is retained in the image memory.

Screen 56 contains code to generate hardcopy images on a DEC Letterwriter dot-matrix printer. GRAPHICS and TERMINATOR send the control code sequences to Letterwriter to turn the graphic print mode on and off. GCR forces a carriage return in the graphic mode. SEGMENT read 6 bytes at (x,y) position in the image memory and converts them into a byte which will cause the Letterwriter to print 6 dots on paper. GLINE thus prints 6 rows of image, and GBLOCK prints a range of rows. GDUMP dumps the entire image memory to the printer. In converting a pixel to a printable dot, the variable stored in #OFFSET is used as a threshold value. If the pixel intensity is greater than #OFFSET, a dot is printed; otherwise, the dot is not printed.

Figure 11 is my own portrait dumped to the printer. Since the aspect ratio of the printer is not corrected, the image is elongated vertically, making my face much thinner than what it should be.

Figure 8. Control and data registers in QVG-123

Figure 9. Control and data register in AF-123

Figure 10. QVG-123 programming procedures

Figure 11. Self portrait

Listing 8. QVG-123 source code

Figure 12. Datacube QVG-123 brochure

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